Dynamic Power Reduction in NOC by Encoding Techniques #IJIRST Journal

Paper Title:- Dynamic Power Reduction in NOC by Encoding Techniques

Abstract:- As technology improve the size will be reduced, and the power dissipated by the links of a network-on-chip (NoC) is starts to participate with the power dissipate by the other element of communication system, for example the routers and the network interfaces (NIs). We design an set of data encoding technique by different schemes to decrease the power dissipation by an links of NoC, which optimizing the on-chip communication system not only in terms of performance but also in terms of power. The idea presented in this paper is base on encoding the packets before they are inserted in to the network in such a way as to minimize both the switching action and the coupling-switching action in the NoC’s link which represent the main factor of power dissipation. These schemes were universal and transparent with respect to the construct NoC fabric that means this application will not require any change in the router and link of architecture. These will be carried in both artificial and real traffic scenario. These effective of the proposed scheme will tolerate to save the energy consumption and power dissipation without changing the performance degradation and with less area consumption in the NI.  

Keywords: switching action, encoding, network-on-chip (NoC), low power, router, Network interfaces (NIs)

I.       Introduction

Moving towards silicon technology node to the next results faster and more efficient gates but slower because there is a more power hungry wires. More than 50% of total dynamic power is dissipate in interconnection in current processor, and this was expected to increase more over in the next several years. Global interconnect length does not scale with smaller transistors and local wires. Chip size remains relatively constant because the chip function continues for instance the RC delay increases exponentially. The RC delay in a 1-mm worldwide wire at the smallest pitch is superior to the intrinsic delay of a two-input NAND fan-out. If the raw computation horsepower seems to be un-limited, thanks to the ability of instance more core’s in a single silicon chip, scalable issue occur, due to making an efficient and reliable communication among the increasing number of core’s, become the real problem. The NOC invent is documented as the most feasible way to tackle with scalable and variability issue that characterize the ultra-deep sub-micron-meter.

Now a days in the on-chip communication issue is relevant, in some of the case more relevant than commutating related issue. The communication sub-system more and more impacts the usual designed objective, and also includes cost (i.e., area of silicon), performances, dissipation of power, consumption of energy and reliability. As technology improves the size is reducing and more fraction of total power is budget of the complex in more core of the system-on-chip (SoC) this is because of communication sub-system.

http://ijirst.org/Article.php?manuscript=IJIRSTV2I4033